The present invention relates to a gallium arsenide (GaAs) semiconductor device comprising an enhancement-mode GaAs field effect transistor (FET) and a depletion-mode GaAs FET (referred to as an enhancement/depletion (E/D) construction), more particularly to an improved method of manufacturing a GaAs semiconductor device of the E/D construction having a heterojunction and utilizing a two-dimensional electron gas.
Direct-coupled FET logic (DCFL) circuits having an E/D construction operate at a low power consumption and are suitable for high integration. Techniques for realizing such circuits by a compound semiconductor are being continually advanced. A simple example of a DCFL circuit is an inverter circuit having an E/D construction.
GaAs semiconductor devices having an E/D construction have been produced by using a GaAs/aluminum gallium arsenide (AlGaAs) heterojunction semiconductor substrate (for example, European patent application No. 82302107.6, i.e., EP-A-0064370). In such GaAs semiconductor devices, the enhancement-mode FET and the depletion-mode FET can operate by utilizing a two-dimensional electron gas generated in the upper portion of an undoped GaAs layer adjoining an N-type AlGaAs layer, i.e., at the interface of the GaAs/AlGaAs heterojunction.
In order to form an enhancement-mode FET and a depletion-mode FET by using the GaAs/AlGaAs semiconductor substrate, it is necessary to obtain an active layer under a gate electrode of each of the FETs having a predetermined thickness. In this case, the active layer means a layer or layers lying between the gate electrode and the GaAs/AlGaAs heterojunction plane. A conventional heterojunction semiconductor substrate comprises a semi-insulating GaAs substrate, an undoped GaAs layer (high purity layer), an N-type AlGaAs layer (electron-supply layer), and an N.sup.+ -type GaAs layer (contact layer), which layers are formed in sequence on the GaAs substrate by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD) method. It is preferable to form an undoped AlGaAs layer between the undoped GaAs layer and the N-type AlGaAs layer, since the undoped AlGaAs layer serves as a buffer and contributes to increasing the electron mobility. For example, the heterojunction semiconductor substrate comprises the above layers having the following thicknesses and impurity concentrations.
______________________________________ Impurity Thickness concentration Layer (nm) (cm.sup.-3) ______________________________________ Undoped GaAs 300 -- Undoped AlGaAs 6 -- N-type AlGaAs 50 1 .times. 10.sup.18 N-type GaAs 50 2 .times. 10.sup.18 ______________________________________
In order to form a gate portion of an enhancement-mode FET in the heterojunction semiconductor substrate, it is preferable to carry out selective etching of the N-type GaAs by just a dry etching method using a reactive gas of CCl.sub.2 F.sub.2. In such selective etching, the etching automatically stops at the surface of the N-type AlGaAs layer. Therefore, an N-type AlGaAs layer having a predetermined thickness for formation of the enhancement-mode FET is formed, so that good uniformity of threshold voltage V.sub.th of enhancement-mode FETs simultaneously formed in a wafer can be attained.
On the other hand, in order to form a gate portion of a depletion-mode FET in the heterojunction semiconductor substrate, a portion of the N-type GaAs layer is etched by a wet chemical etching method so as to form the remaining thickness of the N-type GaAs layer and the thickness of the N-type AlGaAs layer thereunder into a predetermined thickness for formation of the depletion-mode FET. Although attempts have been made to accurately control the etch depth (i.e., the etched quantity) in wet etching, in practice, uniformity of etch depth of depletion-mode FETs simultaneously formed in a wafer is relatively low. Therefore, the uniformity of threshold voltage V.sub.th of the depletion mode FETs is also low.